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The SPI may be accurately described as a synchronous serial interface,1 but it is different from the Synchronous Serial Interface SSI protocol, which is also a four wire synchronous serial communication protocol. SSI Protocol employs differential signaling and provides only a single simplex communication channel. InterfaceeditThe SPI bus specifies five logic signals SCLK Serial Clock output from master. MOSI Master Output Slave Input, or Master Out Slave In data output from master. MISO Master Input Slave Output, or Master In Slave Out data output from slave. SS Slave Select often active low, output from master. While the above pin names are the most popular, in the past alternative pin naming conventions were sometimes used, and so SPI port pin names for older IC products may differ from those depicted in these illustrations Serial Clock Master Output displaystyle rightarrow Slave Input MOSI SIMO, SDO, DI, DIN, SI, MTSR. Master Input displaystyle leftarrow Slave Output MISO SOMI, SDI, DO, DOUT, SO, MRST. Slave Select SS SS, SSEL, CS, CS, CE, n. SS, SS, SS. The MOSIMISO convention requires that, on devices using the alternate names, SDI on the master be connected to SDI on the slave, and vice versa. Slave Select is the same functionality as chip select and is used instead of an addressing concept. Pin names are always capitalized as in Slave Select, Serial Clock, and Master Output Slave Input. OperationeditThe SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action. An example is the Maxim MAX1. Linux Device Drivers, 2nd Edition By Alessandro Rubini Jonathan Corbet 2nd Edition June 2001 0596000081, Order Number 0081 586 pages, 39. 95. ADC, which starts conversion on a highlow transition. With multiple slave devices, an independent SS signal is required from the master for each slave device. Most slave devices have tri state outputs so their MISO signal becomes high impedance logically disconnected when the device is not selected. Devices without tri state outputs cannot share SPI bus segments with other devices only one such slave could talk to the master. Data transmissioneditTo begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. |
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